1. Field of the Invention
Embodiments of the invention relate to a semiconductor device used in a communication element, a digital signal processing field, and an electronic circuit field, and more particularly to a folding analog-to-digital converter.
2. Discussion of the Related Art
A reason to convert an analog signal into a digital signal is to efficiently store, process, and regenerate a signal. With the development of digital technology, almost all information has been recently converted from an analog signal into a digital signal. For this, the analog signal has been converted into the digital signal using an analog-to-digital converter (ADC).
Examples of analog-to-digital converters having characteristics of a high speed and a low power include a flash analog-to-digital converter, a sub-range analog-to-digital converter, a pipeline analog-to-digital converter, and a folding and interpolating analog-to-digital converter.
The flash ADC having the fastest conversion speed among analog-to-digital converters has several defects because of a large number of function blocks and a high input capacity capacitor. To overcome the defects of the flash ADC, a flash ADC implemented by a folding and interpolating circuit technology was proposed. Further, a method for applying the folding and interpolating circuit technology to the sub-range ADC and the pipeline ADC each having a small number of function blocks has been studied. The folding and interpolating ADC was studied based on a bipolar junction transistor (BJT) circuit in an early stage research. In a recent study, as a complementary metal-oxide-semiconductor (CMOS) circuit technology has been recently developed, a CMOS folding and interpolating ADC has been developed.
The structure of the folding and interpolating ADC simultaneously has advantages of the flash ADC in which there is no delay while achieving a high speed, advantages of the sub-range ADC with a small circuit area and low power consumption, and advantages of the pipeline ADC. However, a large number of current sources are necessary in a folding circuit of the folding and interpolating ADC, and thus power consumption of the folding and interpolating ADC greatly increases. Accordingly, a study to reduce the power consumption of the folding and interpolating ADC are being carried out, but has not yet reached a satisfactory result.
FIG. 1 is a block diagram illustrating a basic structure of a folding analog-to-digital converter. As shown in FIGS. 1 and 2, a folding ADC folds an input signal Vin according to a predetermined folding ratio. Then, the folding ADC generates a coarse bit output from a portion of the folded input signal Vin using a coarse converter, and at the same time, generates a fine bit output from a remaining portion of the folded input signal Vin using a fine converter. The coarse converter obtains approximate information showing that a voltage level of the folded input signal belongs to any voltage range, and the fine converter obtains fine bit information using the folded input signal. A digital output is wholly obtained by a sum of the approximate information and the fine bit information. A folding input signal waveform of the folding ADC, as shown in FIG. 2, repeatedly shows an increase waveform and a decrease waveform. As an input of the coarse converter increases, the digital output of the coarse converter monotonously increases in the same manner as the flash ADC. The digital output of the fine converter increases by an interval of one coarse bit and then decreases. In other words, a digital output waveform of the fine converter repeatedly shows an increase waveform and a decrease waveform within an entire input range.
FIG. 3 is a block diagram illustrating a fine converter circuit structure of a folding analog-to-digital converter.
As shown in FIG. 3, a folding ADC 10 includes a reference voltage generating unit 20, an analog pre-processing unit 30, a comparison unit 40, and an encoding unit 50.
The reference voltage generating unit 20 has a plurality of resistors connected in series between a reference voltage source and a ground level voltage source. The reference voltage generating unit 20 divides a reference voltage according to each of resistance ratios to generate a plurality of reference voltages each a different value.
The analog pre-processing unit 30 includes a plurality of folder circuits, each of which performs a processing operation on the plurality of reference voltages generated by the reference voltage generating unit 20 and an analog input signal Vin.
The comparison unit 40 includes a plurality of comparison amplifier, each of which compares a pair of differential outputs received from the analog pre-processing unit 30. The encoding unit 50 converts a digital output signal received from the comparison unit 40 into a binary code to produce n-bit binary code.
As described above, the folding ADC 10 generally requires the reference voltage generating unit 20 having 2n resistors, the analog pre-processing unit 30 having 2n/s folder circuits, the comparison unit 40 having 2n/s comparison amplifiers, etc., so as to obtain n-bit output signal, where “s” is a folding ratio. The folding ratio means the number of zero crossings of a folding signal or the number of pairs of differential signals in one folder circuit of the analog pre-processing unit 30. In the folding ADC 10, the 2n/s folder circuits of the analog pre-processing unit 30 are knows as analog circuits and thus greatly increases power consumption of the folding ADC 10. Further, it is difficult to implement high integration of the folding ADC 10.